I have to admit that ever since the fad in network processors back in the late ‘90s, I’ve been interested in developing hardware for packet processing. This has been at least part of my motivation to learn a Hardware Description Language such as Verilog or VHDL. I remember a time when logic could only be programmed with a soldering iron and wire but I did design some hardware back in the ‘80s using programmable logic and a language called ABLE. But ABLE is like the HDL version of FORTRAN.
The problem with most of the network processors was that they were trying to solve too many problems at the same time. This was an era when Frame Relay was still in common use and ATM was nearing its peek. Designing hardware that could deal with Frame Relay, ATM, MPLS and the Internet Protocols made network processors so complex that they were impracticably difficult to program. They were also physically large, expensive and power hungry.
Two things have changed since then. The capabilities of programmable logic have grown immensely due to their increased density and speed and the quality of development tools. We have a much smaller set of protocols to deal with since the Internet Protocols now dominate networking. This makes it possible to develop more specialized hardware for specific functions such as packet demultiplexing and header check-summing.
Two things came together that got me thinking along these lines. On my way to the Embedded Systems Conference I read the chapter on packet demultiplexing in Network Algorithmics
and a paper about a specific packet demultiplexing scheme called Pathfinder. Pathfinder included a hardware implementation. The other influence was Altera’s booth at the Embedded Systems Conference.
(Disclaimer: my employer is an Altera Certified Design Center Partner). Altera was showing a low cost development kit that they market to schools for logic design courses. The student project was pretty cool. It took two video streams, one from a DVD player and one from a live camera feed and displayed them on one screen with the live feed in the upper left quarter of the screen.
I struck up a conversation with the guy at the booth and he told me about two low cost evaluation kits. One is based on Altera’s Cyclone II FPGA and lists for $150. This kit has the interfaces required if you want to fool around with audio or video signal processing. The second design kit was just announced to support the Cyclone III FPGA. The board includes a high speed interface connector and gobs of RAM. This kit usually lists for $200 but is available at $150 for a short time. Altera has design tools free for download from their website.
What really makes this interesting is that they have a processor core that fits on the Cyclone III and still leaves room for special purpose logic. There are also cores available for Ethernet MAC interfaces. I’m thinking that it could substantially reduce the overhead for processing packets if the MAC interface, packet filtering and check-summing logic and the processor all communicated over on chip busses. The packet headers could be processed in parallel with writing received packets into RAM.
But I’m getting way ahead of myself. I still want to finish a software version before I start designing hardware implementations.